Enhancements
| ATE-1317 | Enable automatic and manual resizing of capacitors in MagnaChip processes. |
| ATE-1327 | Automatically create multiple layout results for sub-blocks of the circuit when there is no existing layout. The top-level floorplan will automatically choose from the available results.
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| ATE-1332 | Support the predefined fill patterns from the user's display.drf in addition to the colors. |
| ATE-1081 | Support for metal enclosure of via rule for TSMC 180 nm process. |
| ATE-1267 | Support diffusion enclosure of gate rule for TSMC 55 nm process. |
ATE-1337
| Allow user to disable recommended high R resistor dummy poly rule for TSMC 22 nm process. |
| ATE-486 | Create routing of all N row simple routing placement cascode current mirrors |
| ATE-1055 | Allow power-downs used to replace end-of-row dummies in current mirrors to be resized to match the end-of-row gate length, width, and number of fingers.
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| ATE-1304 | Route same size resistors that are adjacent (horizontally/vertically).
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Resolved Issues
ATE-1302
| Resolved an issue where zoom location moved when switching back and forth between layout and edit views. |
| ATE-1330 | Fixed an issue with the end-of-row dummies constraint not working in all cases. |
Other Items
ATE-1278, ATE-1334, ATE-1232, ATE-1336, ATE-1338, ATE-1339, ATE-1342, ATE-1343, ATE-1344